fsm_adder.vhd

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library ieee;
use ieee.std_logic_1164.all;

entity fsm_adder is
    generic (
        reg_width : integer := 4
    );
    
    port
    (
        reset : in  std_logic;
        clk : in std_logic;
        
        par_add : in  std_logic;
        serial_active : in std_logic;
        
        a_s : in  std_logic;
        b_s : in  std_logic;
        
        a_p : in  std_logic_vector(reg_width-1 downto 0);
        b_p : in  std_logic_vector(reg_width-1 downto 0);
        
        sum_s : out std_logic;
        sum_p : out  std_logic_vector(reg_width downto 0);
        
        out_valid: out std_logic
    );
end fsm_adder;

architecture fsm_adder_behav of fsm_adder is
    type state_type is (idle, load_data, wait_shift_reg_full, calculate_paralel, data_valid_state, calculate_serial);
    signal state_reg, next_state: state_type;
    
    component shiftreg is
        generic (
            reg_width : integer := 8
        );
        port (
            clk : in std_logic;
            reset : in std_logic;
            load : in std_logic; 
            do_shift : in std_logic;
            sin : in std_logic;
            sout : out std_logic;
            pin : in std_logic_vector(reg_width - 1 downto 0);
            pout : out std_logic_vector(reg_width - 1 downto 0)
        );
    end component;
    
    component serial_adder is
        port
        (
            reset : in  std_logic;
            clk : in std_logic;
            a_s : in  std_logic;
            b_s : in  std_logic;
            sum_s : out std_logic
        );
    end component;
    
    signal load: std_logic;
    signal do_shift: std_logic;
    signal a_s_out: std_logic;
    signal b_s_out: std_logic;
    signal sum_in: std_logic;
    signal generic_pin_for_sum_reg: std_logic_vector(reg_width downto 0);
    
    signal timeout_counter: integer range 0 to reg_width+1;
    
begin
    shift_reg_a: shiftreg generic map (reg_width) port map (clk, reset, load, do_shift, a_s, a_s_out, a_p, pout => open);
    shift_reg_b: shiftreg generic map (reg_width) port map (clk, reset, load, do_shift, b_s, b_s_out, b_p, pout => open);
    shift_reg_sum: shiftreg generic map (reg_width+1) port map (clk, reset, load, do_shift, sum_in, sum_s, generic_pin_for_sum_reg, sum_p);
    generic_pin_for_sum_reg <= (others => '0');
    
    serial_adder_inst: serial_adder port map (reset, clk, a_s_out, b_s_out, sum_in);
    
    fsm_adder_state_transition: process (clk, reset) is
    begin
        if (reset = '1') then
            state_reg <= idle;
        elsif (rising_edge(clk)) then
            state_reg <= next_state;
        end if;
    end process;
    
    fsm_adder_next_state_logic: process (state_reg, par_add, serial_active, timeout_counter) is
    begin
        case (state_reg) is
            when idle =>
                if (par_add = '1') then
                    next_state <= load_data;
                elsif (serial_active = '1') then
                    next_state <= wait_shift_reg_full;
                else
                    next_state <= idle;
                end if;
            
            when load_data =>
                next_state <= calculate_paralel;
            
            when wait_shift_reg_full =>
                if (timeout_counter = 0) then
                    next_state <= calculate_serial;
                else 
                    next_state <= wait_shift_reg_full;
                end if;
            
            when calculate_paralel =>
                if (timeout_counter = 0) then
                    next_state <= data_valid_state;
                else
                    next_state <= calculate_paralel;
                end if;
             
             when calculate_serial =>
                if (serial_active = '0') then
                    next_state <= idle;
                else
                    next_state <= calculate_serial;
                end if;
                
             when data_valid_state =>
                next_state <= idle;
        end case;
    end process;
    
    shift_reg_logic: process (state_reg, next_state, serial_active, timeout_counter) is
    begin
        case (state_reg) is
            when idle =>
                load <= '0';
                do_shift <= '0';
                out_valid <= '0';
            when load_data =>
                load <= '1';
                do_shift <= '0';
                out_valid <= '0';
            when wait_shift_reg_full =>
                load <= '0';
                do_shift <= '1';
                out_valid <= '0';
            when calculate_paralel =>
                load <= '0';
                do_shift <= '1';
                out_valid <= '0';
            when calculate_serial =>
                load <= '0';
                do_shift <= '1';
                if ((timeout_counter /= 0) or (next_state = idle)) then
                    out_valid <= '0';
                else
                    out_valid <= '1';
                end if;
             when data_valid_state =>
                load <= '0';
                do_shift <= '0';
                out_valid <= '1';
        end case;
    end process;
    
    cnt_process: process (clk) is
    begin
        if (rising_edge(clk)) then
            case (state_reg) is
                when load_data =>
                    timeout_counter <= reg_width;
                when wait_shift_reg_full =>
                    if (timeout_counter = 0) then
                        timeout_counter <= reg_width+1;
                    else
                        timeout_counter <= timeout_counter - 1;                    
                    end if;
                when calculate_paralel =>
                    if (timeout_counter /= 0) then
                        timeout_counter <= timeout_counter - 1;                    
                    end if;
                when calculate_serial =>
                    if (timeout_counter /= 0) then
                        timeout_counter <= timeout_counter - 1;                    
                    end if;
                when others =>
                    timeout_counter <= reg_width - 1;
            end case;
        end if;
    end process;
    
end fsm_adder_behav;