shiftreg.vhd

Go to the documentation of this file.

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shiftreg is
    generic (
        reg_width : integer := 8
    );
    port (
        clk : in std_logic;
        reset : in std_logic;
        load, do_shift : in std_logic;
        sin : in std_logic;
        sout : out std_logic;
        pin : in std_logic_vector(reg_width - 1 downto 0);
        pout : out std_logic_vector(reg_width - 1 downto 0)
    );
end shiftreg;

architecture shr_behav_arch of shiftreg is

signal reg_state : std_logic_vector(reg_width - 1 downto 0);

begin

    shift_reg_process : process (clk, reset)
    begin
        if reset = '1' then
            sout <= '0';
            reg_state <= (others => '0');
        elsif rising_edge(clk) then
            if load = '1' then
                reg_state <= pin;
                sout <= pin(0);
            elsif do_shift = '1' then
                sout <= reg_state(1);
                reg_state <= sin & reg_state(reg_width - 1 downto 1);
            end if;
        end if;
        
    end process;

    pout <= reg_state;

end shr_behav_arch;