Serial sequential adder
v.1.0
Example documentation project, author Vladimir Petrović
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A serial shift register with parallel synchronous write and with parallel output. More...
Go to the source code of this file.
Entities | |
shiftreg | entity |
Entitiy declaration for shiftreg. More... | |
shr_behav_arch | architecture |
Behavioral architecture for shiftreg. More... | |
This file describes a simple shift register. It has the entity interface description and one behavioral architechture description. More details about it's interface and implementation can be found in the detail description of entitiy and architecture.
Modified by: Vladimir Petrovic on 11/14/2016
Modification description: Changed shift direction. Previous register shifted bits to the left, this one is shifts data to the right. Also, it is changed that sout is equal to pout(0).
Definition in file shiftreg.vhd.