Serial sequential adder  v.1.0
Example documentation project, author Vladimir Petrović
Entities
shiftreg.vhd File Reference

A serial shift register with parallel synchronous write and with parallel output. More...

Go to the source code of this file.

Entities

shiftreg  entity
 Entitiy declaration for shiftreg. More...
 
shr_behav_arch  architecture
 Behavioral architecture for shiftreg. More...
 

Detailed Description

This file describes a simple shift register. It has the entity interface description and one behavioral architechture description. More details about it's interface and implementation can be found in the detail description of entitiy and architecture.

Author
Strahinja Jankovic
Date
11/08/2016
Version
1.1

Modified by: Vladimir Petrovic on 11/14/2016
Modification description: Changed shift direction. Previous register shifted bits to the left, this one is shifts data to the right. Also, it is changed that sout is equal to pout(0).

Todo:
Check if this shift register can be better combined with other elements in the system in order to reduce the latency between input data and output data.

Definition in file shiftreg.vhd.