shr_behav_arch Architecture Reference

Behavioral architecture for shiftreg. More...

Processes
shift_reg_process	( clk , reset )

Signals
reg_state	std_logic_vector ( reg_width - 1 downto 0 )

Detailed Description

The shifreg's work modes are described in the entity's detail description. Reset is asynchronous, while other signals are processed at every rising edge of clk signal. Paralel load has the higher priority then the serial shift.

Definition at line 52 of file shiftreg.vhd.

Member Function Documentation

shift_reg_process()

shift_reg_process (   clk ,   reset   )

Process

Definition at line 58 of file shiftreg.vhd.

Member Data Documentation

reg_state

reg_state std_logic_vector ( reg_width - 1 downto 0 )

Signal

Definition at line 54 of file shiftreg.vhd.

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The documentation for this class was generated from the following file:

• shiftreg.vhd