shiftreg Entity Reference

Entitiy declaration for shiftreg. More...

Inheritance diagram for shiftreg:

Entities
shr_behav_arch	architecture
	Behavioral architecture for shiftreg. More...

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
reg_width	integer := 8

Ports
clk	in std_logic
reset	in std_logic
load	in std_logic
do_shift	in std_logic
sin	in std_logic
sout	out std_logic
pin	in std_logic_vector ( reg_width - 1 downto 0 )
pout	out std_logic_vector ( reg_width - 1 downto 0 )

Detailed Description

The shift register has a generic reg_width which defines the width of the shift register. Shift register can have two input modes, serial input and paralel input. Register shifts data from serial input sin if the do_shift is 1. After the register is full, first input bit is shown at serial output sout. The shift register has parallel output pout too. If the load signal is active, parallel load is active where the data form input pin is stored in the register. Under reset, all flipflops in shifreg are set to 0. shiftreg's interface is shown in Fig. 1.

Fig. 1. A block symbol of the shiftreg component

Definition at line 32 of file shiftreg.vhd.

Member Data Documentation

clk

clk in std_logic

Port

Definition at line 37 of file shiftreg.vhd.

do_shift

do_shift in std_logic

Port

Definition at line 39 of file shiftreg.vhd.

ieee

ieee

Library

Definition at line 19 of file shiftreg.vhd.

load

load in std_logic

Port

Definition at line 39 of file shiftreg.vhd.

numeric_std

numeric_std

Package

Definition at line 22 of file shiftreg.vhd.

pin

pin in std_logic_vector ( reg_width - 1 downto 0 )

Port

Definition at line 42 of file shiftreg.vhd.

pout

pout out std_logic_vector ( reg_width - 1 downto 0 )

Port

Definition at line 44 of file shiftreg.vhd.

reg_width

reg_width integer := 8

Generic

Definition at line 35 of file shiftreg.vhd.

reset

reset in std_logic

Port

Definition at line 38 of file shiftreg.vhd.

sin

sin in std_logic

Port

Definition at line 40 of file shiftreg.vhd.

sout

sout out std_logic

Port

Definition at line 41 of file shiftreg.vhd.

std_logic_1164

std_logic_1164

Package

Definition at line 21 of file shiftreg.vhd.

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The documentation for this class was generated from the following file:

• shiftreg.vhd