Todo List

File fsm_adder.vhd

Make a better description of the component interface for the Main page. Interface description should be followed with clearer timing diagrams, possibly drawn in MS Visio or any other good quality drawing tools. The timing diagram should have marked timing constraints like in the Fig. 1 of this file.

Class fsm_adder_behav

• finish detailed description of the fsm_adder_behav architecture
  
• comment processes

page Serial sequential adder project documentation

* Describe the structure of the documentation for readers to easily browse through it.

File shiftreg.vhd

Check if this shift register can be better combined with other elements in the system in order to reduce the latency between input data and output data.