fsm_adder.vhd File Reference

A top level design of the system. A serial adder with two working modes. More...

Go to the source code of this file.

Entities
fsm_adder	entity
	Entitiy declaration for fsm_adder component. More...
fsm_adder_behav	architecture
	Behavioral architechture for serial_adder. More...

Detailed Description

Serial adder that can work in two modes: 1. input numbers are loaded using the parallel load of two shift registers and output is stored in output shift register, and 2. when input numbers can be any length and are loaded serially and output is read serially.

Author

Vladimir Petrovic

Date

11/14/2016

Version

1.1

Modified by: Vladimir Petrovic on 11/15/2016
Modification description: TODO section added.

Todo:

Make a better description of the component interface for the Main page. Interface description should be followed with clearer timing diagrams, possibly drawn in MS Visio or any other good quality drawing tools. The timing diagram should have marked timing constraints like in the Fig. 1 of this file.

Fig. 1. A good timing diagram example.

Reference:
AD7908/AD7918/AD7928 - 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP datasheet, Rev. D, Analog Devices, 2010.

Definition in file fsm_adder.vhd.