fsm_adder_behav Architecture Reference

Behavioral architechture for serial_adder. More...

Processes
fsm_adder_state_transition	( clk , reset )
fsm_adder_next_state_logic	( state_reg , par_add , serial_active , timeout_counter )
shift_reg_logic	( state_reg , next_state , serial_active , timeout_counter )
cnt_process	( clk )

Components
shiftreg	<Entity shiftreg>
serial_adder	<Entity serial_adder>

Types
state_type	( idle , load_data , wait_shift_reg_full , calculate_paralel , data_valid_state , calculate_serial )

Signals
state_reg	state_type
next_state	state_type
load	std_logic
do_shift	std_logic
a_s_out	std_logic
b_s_out	std_logic
sum_in	std_logic
generic_pin_for_sum_reg	std_logic_vector ( reg_width downto 0 )
timeout_counter	integer range 0 to reg_width + 1

Instantiations
shift_reg_a	shiftreg <Entity shiftreg>
shift_reg_b	shiftreg <Entity shiftreg>
shift_reg_sum	shiftreg <Entity shiftreg>
serial_adder_inst	serial_adder <Entity serial_adder>

Detailed Description

Sequential.....................

Fig. 1. Block diagram of the sequential serial adder with two work modes.

Fig. 2. State machine of the sequential serial adder with two work modes.

Todo:

• finish detailed description of the fsm_adder_behav architecture
  
• comment processes

Definition at line 87 of file fsm_adder.vhd.

Member Function Documentation

cnt_process()

cnt_process (   clk   )

Process

Definition at line 219 of file fsm_adder.vhd.

fsm_adder_next_state_logic()

fsm_adder_next_state_logic (   state_reg ,   par_add ,   serial_active ,   timeout_counter   )

Process

Definition at line 144 of file fsm_adder.vhd.

fsm_adder_state_transition()

fsm_adder_state_transition	(		clk,
			reset
	)

Definition at line 135 of file fsm_adder.vhd.

shift_reg_logic()

shift_reg_logic (   state_reg ,   next_state ,   serial_active ,   timeout_counter   )

Process

Definition at line 185 of file fsm_adder.vhd.

Member Data Documentation

a_s_out

a_s_out std_logic

Signal

Definition at line 120 of file fsm_adder.vhd.

b_s_out

b_s_out std_logic

Signal

Definition at line 121 of file fsm_adder.vhd.

do_shift

do_shift std_logic

Signal

Definition at line 119 of file fsm_adder.vhd.

generic_pin_for_sum_reg

generic_pin_for_sum_reg std_logic_vector ( reg_width downto 0 )

Signal

Definition at line 123 of file fsm_adder.vhd.

load

load std_logic

Signal

Definition at line 118 of file fsm_adder.vhd.

next_state

next_state state_type

Signal

Definition at line 89 of file fsm_adder.vhd.

serial_adder

serial_adder

Component

Definition at line 107 of file fsm_adder.vhd.

serial_adder_inst

serial_adder_inst serial_adder

Instantiation

Definition at line 133 of file fsm_adder.vhd.

shift_reg_a

shift_reg_a shiftreg

Instantiation

Definition at line 128 of file fsm_adder.vhd.

shift_reg_b

shift_reg_b shiftreg

Instantiation

Definition at line 129 of file fsm_adder.vhd.

shift_reg_sum

shift_reg_sum shiftreg

Instantiation

Definition at line 130 of file fsm_adder.vhd.

shiftreg

shiftreg

Component

Definition at line 91 of file fsm_adder.vhd.

state_reg

state_reg state_type

Signal

Definition at line 89 of file fsm_adder.vhd.

state_type

state_type ( idle , load_data , wait_shift_reg_full , calculate_paralel , data_valid_state , calculate_serial )

Type

Definition at line 88 of file fsm_adder.vhd.

sum_in

sum_in std_logic

Signal

Definition at line 122 of file fsm_adder.vhd.

timeout_counter

timeout_counter integer range 0 to reg_width + 1

Signal

Definition at line 125 of file fsm_adder.vhd.

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The documentation for this class was generated from the following file:

• fsm_adder.vhd