serial_adder Entity Reference

Entitiy declaration for serial_adder. More...

Inheritance diagram for serial_adder:

Entities
serial_add_behav	architecture
	Behavioral and structural architechture for serial_adder. More...

Libraries
ieee

Use Clauses
std_logic_1164

Ports
reset	in std_logic
	Sequential circuit reset signal.
clk	in std_logic
	clk signal
a_s	in std_logic
	Serial input 1.
b_s	in std_logic
	Serial input 2.
sum_s	out std_logic
	Serial output sum.

Detailed Description

Serial adder is a sequential component that adds two N-bit input binary numbers and gives a N+1-bit result. Input and output data are set serially, bit by bit. The result is calculated bit by bit, as the input numbers' bits are set. Input numbers' bits are set at every rising edge of the input clock. The serial_adder stores output carry of one binary addition and uses it as input carry in the calculation of next output bit. serial_adder's interface is shown in Fig. 1.

Fig. 1. A block symbol of the serial_adder component

Definition at line 27 of file serial_adder.vhd.

Member Data Documentation

a_s

a_s in std_logic

Port

Definition at line 36 of file serial_adder.vhd.

b_s

b_s in std_logic

Port

Definition at line 38 of file serial_adder.vhd.

clk

clk in std_logic

Port

Definition at line 33 of file serial_adder.vhd.

ieee

ieee

Library

Definition at line 16 of file serial_adder.vhd.

reset

reset in std_logic

Port

Definition at line 31 of file serial_adder.vhd.

std_logic_1164

std_logic_1164

Package

Definition at line 17 of file serial_adder.vhd.

sum_s

sum_s out std_logic

Port

Definition at line 42 of file serial_adder.vhd.

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The documentation for this class was generated from the following file:

• serial_adder.vhd