serial_adder.vhd

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library ieee;
use ieee.std_logic_1164.all;

entity serial_adder is
    port
    (
        reset : in  std_logic;
        clk : in std_logic;
        
        a_s : in  std_logic;
        b_s : in  std_logic;
        
        sum_s : out std_logic
    );
end serial_adder;

architecture serial_add_behav of serial_adder is
    -- state definitions
    type state_type is (cout_0, cout_1); 
    
    -- signal definitions
    signal state_reg, next_state: state_type;
    
    signal carry_out: std_logic;
    signal carry_in: std_logic;
    
    -- components declaration
    component fulladder is
    port
    (
        a : in  std_logic;
        b : in  std_logic;
        cin : in  std_logic;
        s : out std_logic;
        cout : out std_logic
    );
    end component;
    
    
begin
    FA: fulladder port map (a_s, b_s, carry_in, sum_s, carry_out);
    
    serial_adder_state_transition: process(reset,clk) is
    begin 
        if (reset = '1') then
            state_reg <= cout_0;
        elsif (rising_edge(clk)) then
            state_reg <= next_state;
        end if;
    end process;
    
    serial_adder_next_state_logic: process (carry_out) is
    begin
        if (carry_out = '0') then
            next_state <= cout_0;
        else
            next_state <= cout_1;
        end if;
    end process;
    
    carry_in <= '0' when state_reg = cout_0 else
                '1' when state_reg = cout_1;
       
end serial_add_behav;