fulladder.vhd

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library ieee;
use ieee.std_logic_1164.all;


entity fulladder is
    port
    (
        a : in  std_logic;
        b : in  std_logic;
        cin : in  std_logic;
        
        s : out std_logic;
        cout : out std_logic
    );
end fulladder;

architecture fa_behav of fulladder is
begin
    s <= (a xor b) xor cin;
    cout <= (a and b) or (cin and (a xor b));
end fa_behav;