fulladder Entity Reference

Entitiy declaration for fulladder. More...

Inheritance diagram for fulladder:

Entities
fa_behav	architecture
	Behavioral architechture for fulladder. More...

Libraries
ieee

Use Clauses
std_logic_1164

Ports
a	in std_logic
	Input bit 1.
b	in std_logic
	Input bit 2.
cin	in std_logic
	Input carry.
s	out std_logic
	Output sum.
cout	out std_logic
	Output carry.

Detailed Description

Full adder is a simple combinational circuit that adds two input signals a and b and an input carry signal cin to a sum s and output carry signal cout. Fulladder's interface is shown in Fig. 1.

Fig. 1. A block symbol of the fulladder component

Definition at line 18 of file fulladder.vhd.

Member Data Documentation

a

a in std_logic

Port

Definition at line 22 of file fulladder.vhd.

b

b in std_logic

Port

Definition at line 24 of file fulladder.vhd.

cin

cin in std_logic

Port

Definition at line 26 of file fulladder.vhd.

cout

cout out std_logic

Port

Definition at line 32 of file fulladder.vhd.

ieee

ieee

Library

Definition at line 1 of file fulladder.vhd.

s

s out std_logic

Port

Definition at line 29 of file fulladder.vhd.

std_logic_1164

std_logic_1164

Package

Definition at line 2 of file fulladder.vhd.

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The documentation for this class was generated from the following file:

• fulladder.vhd