Serial sequential adder
v.1.0
Example documentation project, author Vladimir Petrović
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Go to the source code of this file.
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FAMILY | " Cyclone V " |
DEVICE | 5CSEMA5F31C6 |
TOP_LEVEL_ENTITY | fsm_adder |
ORIGINAL_QUARTUS_VERSION | 15 . 1 . 2 |
PROJECT_CREATION_TIME_DATE | " 23 : 59 : 13 NOVEMBER 15 , 2016 " |
LAST_QUARTUS_VERSION | 15 . 1 . 2 |
VHDL_FILE | shiftreg.vhd |
VHDL_FILE | serial_adder.vhd |
VHDL_FILE | fulladder.vhd |
VHDL_FILE | fsm_adder.vhd |
PROJECT_OUTPUT_DIRECTORY | output_files |
MIN_CORE_JUNCTION_TEMP | 0 |
MAX_CORE_JUNCTION_TEMP | 85 |
ERROR_CHECK_FREQUENCY_DIVISOR | 256 |
EDA_SIMULATION_TOOL | " ModelSim-Altera ( VHDL ) " |
EDA_OUTPUT_DATA_FORMAT | VHDL -section_id eda_simulation |
PARTITION_NETLIST_TYPE | SOURCE -section_id Top |
PARTITION_FITTER_PRESERVATION_LEVEL | PLACEMENT_AND_ROUTING -section_id Top |
PARTITION_COLOR | 16764057 -section_id Top |
PARTITION_HIERARCHY | root_partition -to | -section_id Top |
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Definition at line 41 of file fsm_adder.qsf.
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Definition at line 47 of file fsm_adder.qsf.
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Definition at line 48 of file fsm_adder.qsf.
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Definition at line 49 of file fsm_adder.qsf.