Nivoi apstrakcije i reprezentacije

• Funkcionalni nivo (Behavioral)
• Nivo ponašanja (Behavioral)
• Tok podataka (Dataflow)
• Algoritamski (Algorithmic)
• Stukturni nivo (Structural)
• Fizički nivo (Physical) - implementacija

Nivo ponašanja

• Služi sa opisivanje ponašanja sistema
• "Šta sistem radi?"
• Veza između ulaznih i izlaznih signala

Strukturni nivo

Opis sistema kao skup logičkih kola i komponenti koje su povezane i obavljaju određenu funkciju

Primer

Lopovi i automobil na daljinsko upravljanje (OE2ODE)

Nivo ponašanja

Za kretanje unapred

$$an = \overline{pn} \cdot (\overline{obrnuto}\cdot un + obrnuto\cdot uu)$$

Strukturni nivo

Entity

entity NAME_OF_ENTITY is [ generic (generic_declarations);]
	port (signal_names: mode type;
	      signal_names: mode type;
		.
		.
	      signal_names: mode type);
end [NAME_OF_ENTITY] ;
						

Automobil

entity automobil is
	port (pn, obrnuto, un, uu: in std_logic;
	      an: out std_logic);
end automobil;
						

Architecture

architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
	-- components declarations
	-- signal declarations
	-- constant declarations
	-- functions declarations
	-- procedure declarations
	-- type declarations
	.
	.
begin
-- Statements
	.
	.
end architecture_name;
						

Automobil - nivo ponašanja

architecture behavioral of automobil is
begin
	an <= (not pn) and (((not obrnuto) and un) or (obrnuto and uu));
end behavioral;
						

Automobil - strukturni nivo

architecture structural of automobil is
	-- Declarations
	component AND2
		port (in1, in2: in std_logic;
		      out1: out std_logic);
	end component;
	component OR2
		port (in1, in2: in std_logic;
		      out1: out std_logic);
	end component;
	component NOT1
		port (in1: in std_logic;
		      out1: out std_logic);
	end component;
	-- signals
	signal npn, nobrnuto, y1, y2, y3: std_logic;
begin
	-- component initiation
	U0: NOT1 port map (pn, npn);
	U1: NOT1 port map (obrnuto, nobrnuto);
	U2: AND2 port map (nobrnuto, un, y1);
	U3: AND2 port map (obrnuto, uu, y2);
	U4: OR2 port map (y1, y2, y3);
	U5: AND2 port map (npn, y3, an);
end structural;
						

Signali

signal list_of_signal_names: type [ := initial value] ;
						

Deklarisani izvan procesa!

Promena se vrsi sa kasnjenjem i tek na kraju procesa!

signal_name <= expression;
						

Varijable

variable list_of_variable_names: type [ := initial value] ;
						

Deklarisane samo unutar procesa (ili u funkcijama i procedurama)!

Promena se vrši istog trenutka.

Nemaju fizičku reprezentaciju u kolu.

variable_name := expression;
						

Bitna razlika!

Pseudokod primer

a1 = 1;
a2 = 2;
a3 = 3;

a1 = a2;
a2 = a1 + a3;
a3 = a2;
rezultat = a1 + a2 + a3;
						

Signali

architecture SIGN of EXAMPLE is
     signal TRIGGER, RESULT: integer := 0;
     signal signal1: integer :=1;
     signal signal2: integer :=2;
     signal signal3: integer :=3;
begin
     process   
     begin
           wait on TRIGGER;
           signal1 <= signal2;
           signal2 <= signal1 + signal3;
           signal3 <= signal2;
           RESULT  <= signal1 + signal2 + signal3;
     end process;
end SIGN;
						

Varijable

architecture VAR of EXAMPLE is
     signal TRIGGER, RESULT: integer := 0;
begin
     process
           variable variable1: integer :=1;
           variable variable2: integer :=2;
           variable variable3: integer :=3;
     begin
           wait on TRIGGER;
           variable1 := variable2;
           variable2 := variable1 + variable3;
           variable3 := variable2;
           RESULT <= variable1 + variable2 + variable3;
     end process;
end VAR
						

If-Elsif-Else

entity MUX_4_1 is
   port (S1, S0, A, B, C, D: in std_logic;
           Z: out std_logic);
   end MUX_4_1;
architecture behav_MUX41 of MUX_4_1 is
begin
   P1: process (S1, S0, A, B, C, D)
   begin
     if (( not S1 and not S0 )=’1’) then
           Z <= A;
     elsif (( not S1 and S0) = ‘1’) then
           Z<=B;
     elsif ((S1 and not S0) =’1’) then
           Z <=C;
     else
           Z<=D;
end if;
   end process P1;
end behav_MUX41;
						

Case-When

entity MUX_4_1 is
   port ( SEL: in std_logic_vector(1 downto 0);
           A, B, C, D: in std_logic;
           Z: out std_logic);
   end MUX_4_1;
architecture behav_MUX41 of MUX_4_1 is
begin
   PR_MUX: process (SEL, A, B, C, D)
   begin
     case SEL is
           when “00” => Z <= A; 
           when “01” => Z <= B;      
           when “10” => Z <= C;                  
           when “11” => Z <= D;
           when others => Z <= ‘X’;
     end case;
   end process PR_MUX;
end behav_MUX41;
						

Signal-When

entity MUX_4_1_Conc is
   port (S1, S0, A, B, C, D: in std_logic;
           Z: out std_logic);
   end MUX_4_1_Conc;
architecture concurr_MUX41 of MUX_4_1_Conc is
begin
	 Z <= A when S1=’0’ and S0=’0’ else
	      B when S1=’0’ and S0=’1’ else
	      C when S1=’1’ and S0=’0’ else
	      D;
end concurr_MUX41;
						

With-Select

entity MUX_4_1_Conc2 is
   port (A, B, C, D: in std_logic;
           SEL: in std_logic_vector(1 downto 0);
           Z: out std_logic);
   end MUX_4_1_Conc2;
architecture concurr_MUX41b of MUX_4_1_Conc2 is
begin
     with SEL select
                Z <= A when “00”,
		     B when “01”,
		     C when “10”,
		     D when “11”;
end concurr_MUX41b;