-- Copyright (C) 2019 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. -- *************************************************************************** -- This file contains a Vhdl test bench template that is freely editable to -- suit user's needs .Comments are provided in each section to help the user -- fill out necessary details. -- *************************************************************************** -- Generated on "11/24/2019 12:02:29" -- Vhdl Test Bench template for design : moving_square -- -- Simulation tool : ModelSim-Altera (VHDL) -- LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_textio.all; use std.textio.all; ENTITY moving_square_vhd_tst IS END moving_square_vhd_tst; ARCHITECTURE moving_square_arch OF moving_square_vhd_tst IS -- constants constant CLK_PERIOD : time := 20 ns ; constant VGA_CLK_PERIOD : time := 15.3846 ns ; -- signals SIGNAL clk_50MHz : STD_LOGIC :='1'; SIGNAL mod_xspeed : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL mod_yspeed : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL reset : STD_LOGIC; SIGNAL VGA_B : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL VGA_BLANK_N : STD_LOGIC; SIGNAL VGA_CLK : STD_LOGIC; SIGNAL VGA_G : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL VGA_HS : STD_LOGIC; SIGNAL VGA_R : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL VGA_SYNC_N : STD_LOGIC; SIGNAL VGA_VS : STD_LOGIC; COMPONENT moving_square PORT ( clk_50MHz : IN STD_LOGIC; mod_xspeed : IN STD_LOGIC_VECTOR(1 DOWNTO 0); mod_yspeed : IN STD_LOGIC_VECTOR(1 DOWNTO 0); reset : IN STD_LOGIC; VGA_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); VGA_BLANK_N : OUT STD_LOGIC; VGA_CLK : OUT STD_LOGIC; VGA_G : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); VGA_HS : OUT STD_LOGIC; VGA_R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); VGA_SYNC_N : OUT STD_LOGIC; VGA_VS : OUT STD_LOGIC ); END COMPONENT; BEGIN i1 : moving_square PORT MAP ( clk_50MHz => clk_50MHz, mod_xspeed => mod_xspeed, mod_yspeed => mod_yspeed, reset => reset, VGA_B => VGA_B, VGA_BLANK_N => VGA_BLANK_N, VGA_CLK => VGA_CLK, VGA_G => VGA_G, VGA_HS => VGA_HS, VGA_R => VGA_R, VGA_SYNC_N => VGA_SYNC_N, VGA_VS => VGA_VS ); clk_50MHz <= not clk_50MHz after CLK_PERIOD/2; always : PROCESS BEGIN reset <= '1'; wait for 2*VGA_CLK_PERIOD; reset <= '0' ; wait for 2*VGA_CLK_PERIOD; mod_xspeed <= "01"; mod_yspeed <= "01"; wait for VGA_CLK_PERIOD; mod_xspeed <= "00"; mod_yspeed <= "00"; wait for VGA_CLK_PERIOD; mod_xspeed <= "01"; mod_yspeed <= "01"; wait for VGA_CLK_PERIOD; mod_xspeed <= "00"; mod_yspeed <= "00"; wait for VGA_CLK_PERIOD; mod_xspeed <= "01"; mod_yspeed <= "01"; wait for VGA_CLK_PERIOD; mod_xspeed <= "00"; mod_yspeed <= "00"; wait for VGA_CLK_PERIOD; mod_xspeed <= "01"; mod_yspeed <= "01"; wait for VGA_CLK_PERIOD; mod_xspeed <= "00"; mod_yspeed <= "00"; wait for VGA_CLK_PERIOD; mod_xspeed <= "01"; mod_yspeed <= "01"; wait for VGA_CLK_PERIOD; mod_xspeed <= "00"; mod_yspeed <= "00"; wait for VGA_CLK_PERIOD; WAIT; END PROCESS always; process (VGA_CLK) file file_pointer: text open WRITE_MODE is "D:\vga-03-moving\vga_signals.txt"; variable line_el: line; begin if rising_edge(VGA_CLK) then -- Write the time --write(line_el, now); -- write the line. write(line_el, now/ns); -- write the line. write(line_el, string'(" ns:"));-- write the line. -- Write the hsync write(line_el, string'(" ")); write(line_el, std_logic(VGA_HS)); -- write the line. -- Write the vsync write(line_el, string'(" ")); write(line_el, std_logic(VGA_VS)); -- write the line. -- Write the red write(line_el, string'(" ")); write(line_el, std_logic_vector(VGA_R)); -- write the line. -- Write the green write(line_el, string'(" ")); write(line_el, std_logic_vector(VGA_G)); -- write the line. -- Write the blue write(line_el, string'(" ")); write(line_el, std_logic_vector(VGA_B)); -- write the line. writeline(file_pointer, line_el); -- write the contents into the file. end if; end process; END moving_square_arch;